1. Field of the Invention
The present invention relates to a nonvolatile semiconductor storage apparatus.
2. Description of the Related Art
One known nonvolatile semiconductor storage apparatus is a floating-gate type flash memory. Data is written to a floating-gate type flash memory by injecting charges to a floating gate to change a threshold voltage of a MOS transistor.
FIG. 7 is a circuit diagram showing an important part of a conventional floating-gate type flash memory 700.
In the flash memory 700, a plurality of memory cells M111 through M11j are arranged within a matrix. Each memory cell includes a MOS transistor having a floating gate. In the flash memory 700, a plurality of word lines and a plurality of source lines oriented along a row direction are alternately located and a plurality of bit lines are oriented along a column direction.
In order to simplify the description, FIG. 7 shows j memory cells M111 through M11j which are connected to one word line WL1.
Furthermore, in order to simplify the description, FIG. 7 shows one memory cell connected to each bit line, but in the whole flash memory 700, a plurality of memory cells are connected to each bit line.
Gates of the respective j MOS transistors located along the row direction are connected to a common word line WL11. Sources of the MOS transistors are connected to a common source line S11. More specifically, the source line S11 is shared by the plurality of memory cells M111 through M11j. 
Drains of a plurality of MOS transistors are respectively connected to each bit line Bit11 through Bit1j. 
For writing data into a memory cell, one of the bit lines Bit11 through Bit1j is selected by a selector 11. A write voltage is applied to the memory cell connected to the selected bit line via the selected bit line.
Besides the floating-gate type flash memory, a ferromagnetic memory is known as another type of nonvolatile semiconductor storage apparatus. A ferromagnetic memory uses a variable resistance element which is capable of selecting an electric resistance value by selecting a magnetization direction of a ferromagnet. The ferromagnetic memory is also referred to as an MRAM (magnetic random access memory).
FIG. 8 is a circuit diagram showing an important part of a conventional ferromagnetic memory 800.
The ferromagnetic memory 800 is a 1T1R (one-transistor-one-resistance) type memory using a variable resistance element. Such a ferromagnetic memory 800 is described in, for example, Japanese Laid-Open Publication No. 2002-140889.
In the ferromagnetic memory 800, a plurality of memory cells M111 through M11j are arranged within a matrix. Each of the memory cells includes an n-type MOS transistor which acts as a current control element and a variable resistance element.
In the ferromagnetic memory 800, a plurality of word lines and a plurality of source lines oriented along a row direction are alternately located and a plurality of bit lines are respectively oriented along a column direction.
In order to simplify the description, FIG. 8 shows j memory cells M111 through M11j which are connected to one word line WL11.
Furthermore, FIG. 8 shows one memory cell connected to each bit line, but in the whole ferromagnetic memory 800, a plurality of memory cells are connected to each bit line.
Gates of the respective plurality of MOS transistors 111a through 11ja located along the row direction are connected to a common word line WL11. Sources of the MOS transistors 111a through 11ja are connected to a common source line S11 via variable resistance elements 111b through 11jb corresponding to the MOS transistors. More specifically, the source line S11 is shared by the plurality of memory cells M111 through M11j. 
Drains of a plurality of MOS transistors 111a through 11ja are respectively connected to each bit line Bit11 through Bit1j. 
For writing data into a memory cell, one of the bit lines Bit11 through Bit1j is selected by a selector 11. A write voltage is applied to the memory cell connected to the selected bit line via the selected bit line.
In the floating-gate type flash memory 700 of FIG. 7, charges are injected to a floating gate as follows. A voltage is applied to a gate of a MOS transistor via a word line, for example. Also, a voltage is applied to a drain of the MOS transistor via a bit line. A source of the MOS transistor is connected to a ground voltage Vss via a source line. Thus, hot electrons are generated near the drain of the MOS transistor.
Herein, when a resistance value of a source line per memory cell is assumed to be R0, a cumulative resistance value of the source line at the memory cell M111, for example, is (R0×j). The cumulative resistance value of the source line at the memory cell M11j is R0. Thus, the cumulative resistance value at the memory cell M111 is j times the cumulative resistance value at the memory cell M11j. 
Such a difference in the cumulative resistance values of the source line at memory cells causes problems such as differences in source-drain potentials of the MOS transistors and a variation in threshold voltages (ON resistances).
Similar to the flash memory 700 described above, in the ferromagnetic memory 800 using a variable resistance element of FIG. 8, cumulative resistance values of the source line at each of memory cells vary depending on the position of the memory cell. Thus, for example, after the same data value is written to two different memory cells, a variance in states of the memory cells (more specifically, resistance values of the variable resistance element) is generated.
Such a variance in the memory cell states may be a big problem particularly when a multi-level technique is introduced so that a memory cell can store three or more data values. This problem will be described in detail below with reference to FIGS. 9A and 9B.
FIG. 9A is a graph showing a probability distribution of resistance values of a memory cell which is capable of storing two data values. FIG. 9B is a graph showing a probability distribution of resistance values of a memory cell which is capable of storing four data values. In FIGS. 9A and 9B, horizontal axes indicate resistance values of memory cells and vertical axes indicate probability distributions.
As shown in FIG. 9A, in the case where a memory cell is capable of storing two data values, resistance values of memory cells are required to be within two ranges, i.e., a range from Ra to Ra′ and a range from Rb to Rb′. A memory cell having a resistance value within the range from Ra to Ra′ is allocated with data value “0”. A Memory cell having a resistance value within the range from Rb to Rb′ is allocated with data value “1”.
As shown in FIG. 9B, in the case where a memory cell is capable of storing four data values, resistance values of memory cells are required to be within four ranges, i.e., a range from R1 to R1′, a range from R2 to R2′, a range from R3 to R3′, and a range from R4 to R4′. A memory cell having a resistance value within the range from R1 to R1′ is allocated with data value “0”. A memory cell having a resistance value within the range from R2 to R2′ is allocated with data value “1”. A memory cell having a resistance value within the range from R3 to R3′ is allocated with data value “2”. A memory cell having a resistance value within the range from R4 to R4′ is allocated with data value “3”.
In general, a maximum and a minimum resistance values of a memory cell are fixed. Thus, Ra=R1 and Rb′=R4′. Accordingly, in a memory cell which is capable of storing four data values, the resistance values of the memory cell should be controlled within a narrower range than in a memory cell which is capable of storing two data values.
Therefore, when differences in cumulative resistance values of a source line at each of the memory cells is generated in accordance with the positions of the memory cells, and thus a variance in states of memory cells is generated, resistance values may not fall within narrow permissible ranges of each of the states. Thus, incorrect data may be obtained.
In a conventional nonvolatile semiconductor storage apparatus, irrespective of positions of memory cells, a constant voltage is applied to a source line. Thus, it is not easy to suppress a variance in cumulative resistance values of the source line at each of the memory cells in accordance with the positions of the memory cells. In particular, as a capacity of a memory is increased and a multi-level technique is introduced as a method for increasing a capacity, it is required to reduce a variance in resistance values of each of the storage states.